CMOS-Basic

Nanometer CMOS ICs basics

Information

A 3-day tutorial on the development of CMOS ICs. For engineers working in electronic product development and engineering, who have to write and read IC specifications, test samples, discuss technical details with suppliers and customers, etc. and for others who need a thorough understanding of ICs.

 

Developing CMOS ICs is a complex process requiring dedicated expertise. Engineers who supervise the design of an IC, need to have a thorough understanding of ICs, the possibilities and impossibilities of IC technology. The course gives an overview of the basics, physics, fabrication, design and applications of CMOS ICs into the nanometer range. It also discusses technology/design scaling bottlenecks to and even beyond 32nm CMOS and is also meant to close the gap between the product development/engineering, design, test and technology communities. The course focuses on CMOS-ICs as 90% of ICs are made in this technology.

Intended for

This course is meant as a comprehensive tutorial on selected subjects of state-of-the-art CMOS ICs for engineers working in electronic product development and engineering and those who have to write and read product specifications, test samples, discuss technical details with suppliers and customers, etc. and others who need an thorough understanding of chip development. Level: Technical college or university level.

Programme

Basic principles

MOS physics. Characteristics. Equations. Capacitances (short summary).

Geometry effects 

Temperature behaviour. Subthreshold behaviour and leakage current mechanisms.

CMOS technology

Lithography summary. Basic CMOS processing steps. From a basic nMOS process to a 45 nm CMOS process.

CMOS design

Basic principles of electrical and logic design.

CMOS memories

Memory architectures, SRAM, DRAM, ROM, PROM, E(E)PROM, NAND- and NOR-flash memories, stand-alone and embedded memories.

VLSI and ASICs

Design flow. Hierarchy levels. IP cores. Re-use. ASICs.

Low-power

Battery overview. Summary of existing technology and design options for low power and low leakage.

Robustness of ICs

Reliability and signal integrity issues. Latch-up, Punch-through, ESD protection circuits. Hot-carrier degradation. Electromigration. NBTI. Supply and substrate noise, power integrity, decoupling, cross-talk, noise margins, EMC, soft-errors and variability, etc.

Testing, debugging, failure analysis and yield, packaging

Testing. Basics of yield and simple model. Packaging characteristics and trends, Diagnosis techniques, state-of-the-art failure analysis techniques. Repair, focused ion beam, etc.

Scaling trends and roadblocks

Costs and roadblocks for 65 nm technologies and beyond. Speed and power trends. Design, masks and processing costs. Roadblocks and solutions. End of Moore’s Law!

 

Methods: lectures, exercises. Course material: book. Award: certificate.

Timetable

03-12-2012 08:30
04-12-2012 08:30
05-12-2012 08:30