SI-WS

Signal integrity - workshop

Information

As systems get faster, signal integrity may become a problem. In this workshop, for electronic designers, board– and IC designers, the theory behind signal integrity is explained, practical problems are modeled and simulated, and solutions are discussed.

 

The "fast edges" of modern electronic devices cause a lot of signal integrity problems. It is more and more difficult to use those components within their own specification. This will result in unexpected behavior of the hardware, reset problems, download problems, latch-ups, software hang-ups caused by the hardware and, last but not least, very noisy boards not compliant to FCC (USA), CISPR (EU) or VCCI (Japan). The course concentrates on signal integrity on the PCB and around the interface between board and IC. It does not cover aspects as architectures for fast systems.

 

After the course, the participant will: 

• be able to recognize the signal integrity problems of modern fast electronics systems; 
• know and be able to apply methods to improve the signal integrity of PCB's;
• know IC characteristics that will cause signal integrity problems at a PCB.

 

Intended for

This workshop is primarily meant for system architects, electronic designers as well as board- and IC-designers. At least a BSc in electronics/ electrical engineering and a working relation with EMC.

Programme

Signal integrity problems may arise at many levels: within an IC, through the package, on a PCB, at the backplane of boards, at inter-system communication.

There are common themes at the various levels. But there are also practical considerations that cause different approaches at different levels. This course concentrates on signal integrity on the PCB and around the interface between IC and PCB. The issue is highly relevant for both the PCB designer and the IC designer. The examples in the course applied, however, stem from the PCB area.

 

There are problems on signal integrity and power integrity that manifest themselves on a PCB but that should have been resolved in an IC. In case an IC radiates strongly (EMC), there are additional costs at PCB-level such as with housing or a metal shield, possibly the performance may even have to be reduced. To prevent these problems the PCB designer might choose a chip set from another supplier.

 

Furthermore, a relationship may exist between the pinning of an IC and the number of layers of a PCB. For financial reasons there is a strong preference for e.g. a 4 layers above a 6 layers PCB (costs are rising sharply with the number of layers). However, this can make demands on the pinning. If these demands are not handled properly, a 6 layer PCB might be necessary because of SI reasons. An alternative is to select an IC from another supplier.

 

Theoretical parts:

• Signal integrity: high speed signal propagation, reflection, ringing, transmission-lines, termination, balanced lines, cross-talk, stack-up, simulation of high speed nets.
• Power integrity: high speed power distribution, power planes topology, board stack-up, bypassing capacitors, PCB production and materials, power supply noise classes, power integrity simulation demo. 
• IBIS modeling: creating IBIS models, modifying models, understanding the most important parameters of an IBIS model. 
• EMC introduction: EMC compliance tests, emission, immunity to RF fields, EFT, bursts, pre-compliance testing, ESD, latch-up.
• EMC signals: identify the sources of radiation, narrow spectra signals versus wide spectra signals, board stack-up improvements for EMC. 
• EMC coupling and cabling: ground bounce, optimization of cable connections to a board, antenna’s, radiation gain caused by cavities.
• EMC advanced partitioning: noise classes, SNR, tuners high SNR, dynamic range improvements, shielding and why very often partly shielding will not help. 
• High volume Electronics: cost-price optimized designs, 2-layer boards for high speed, 4 layer boards, board production costs. 
• High speed memory connection: DDRx and SSTL.

 

Practical parts:

• Transmission line termination simulations, simulation of different board stack-ups.
• IBIS modeling, IBIS modeling theory, debugging IBIS models + IBIS editor.
• Topology simulation, board partitioning, crosstalk.

 

Methods: lectures, PC exercises. Course material: course notes. Award: certificate.

Timetable

11-09-2012 12:00
18-09-2012 12:00
25-09-2012 12:00