Integrated circuits are manufactured by a long sequence of high-precision and hence defect prone processing steps. Hence, every individual semiconductor product needs to undergo stringent electrical tests to weed out the defective parts and guarantee outgoing product quality to the customer. The field of ‘Design-for-Test’ (DfT) focuses in the broad sense on developing economically adequate tests for ICs. Those tests need to assure sufficient qualityat acceptable test application costs, corresponding to the target application area (e.g., wireless consumer products have less stringent quality requirements, but also different test cost budgets than medical or aerospace products). As no IC can be released into highvolume production without an adequate manufacturing test, acceptable test development time is also of key importance. 

Structural testing, in which tests are generated based on well-accepted defect-abstracting fault models, have largely replaced the traditional functional tests, because they can be generated automatically in relatively short time, achieve objectively better defect coverage, and (in case of failing tests) allow diagnosis algorithms to pinpoint the type and location of the failure root cause. The latter enables automatic high-volume diagnosis to create process learning and yield improvement. One of the main challenges in IC testing is the limited accessibility from the chip pins into theinternal circuitry inside the IC. To improve controllability and observability, extra ‘DfT hardware’ is added to the functional circuitry; this typically amounts to 5-10% of the silicon area. Scan design is the most commonly practiced form of DfT design, whereby a test mode is added in which functional registers are concatenated into one or more shift registers that are accessible from the external test equipment. More advanced forms of DfT hardware include (i) ‘wrappers’ that allow modular testing of increasingly complex chips, (ii) on-chip decompression of test stimuli and compression of test responses, (iii) circuitry that tests parts othe IC itself without the need for external test equipment (‘built-in self-test’ or BIST), and (iv) on-chip features for the benefit of the chip user.   
This course, presented by a world-renowned speaker in the field with broad scientific and industrial experience, covers the fundamentals of IC test and DfT. The speaker has presented his course material at many international conferences, as well as to practicing engineers during in-house courses.

This training is available for open enrollment as well as for in-company sessions. For in-company sessions, the training can be adapted to your situation and special needs.


After the course, the participant will:

  • understand the role and importance of testing for manufacturing defects in the overall IC product creation process;
  • have a good understanding of the functions of IC test equipment;
  • know the IC defect types and their associated fault models;
  • know for digital logic, the concept of Automatic Test Pattern Generation for stuck-at faults, and have an understanding of advanced tests such as delay-fault testing and IDDQ testing;
  • know for (embedded) memories, the concept of techniques applied such as March Tests;
  • know techniques to make the digital portion of an IC testable: scan design, wrapper and Test Access Mechanism (TAM) design, Test Data Compression (TDC), and Built-In SelfTest (BIST);
  • know the role of failure analysis and diagnosis, and the concepts of techniques applied;
  • the principles of board-level testing and common on-chip facilities for that, in particular IEEE Std 1149.1 (JTAG);
  • be able to make a reasoned choice from available IC tests and Design-for-Test (DfT) techniques;
  • be able to follow other IC test courses and tool trainings more effectively.

Intended for

This course is intended for those involved in design-for-test (DfT) and test of digital integrated circuits (ICs): Digital IC design engineers, test and product engineers, fab engineers, test engineers, starting DfT engineers. Also: test researchers, test methodology developers, test tool developers and their managers!

Required background knowledge:

  • Educational level: technical college / university in Electrical engineering, Computer, engineering or mathematics;
  • Familiarity with digital synchronous IC design and manufacturing;
  • Recommended: Several years of industrial practice.
Start date Expected Q2 2024
Duration 3 days in 1 week
Price per participant € 1,790 excl. VAT *
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  • Introduction to IC Testing;
  • Test Execution: Equipment & Flows;
  • Defects and Faults;
  • Automatic Test Pattern Generation;
  • Scan Design;
  • Memory Testing;
  • Diagnosis and Failure Analysis;
  • PCB Testing and Boundary Scan Design;
  • Advanced Fault Models and Tests (Testing for Shorts: VLV & IDDQ Testing, Delay Testing, Strengthening Stuck-At testing);
  • In-Field Defects: Reliability Issues and Soft Errors;
  • Test Cost Reduction;
  • Modular (Core-Based) SOC Testing and IEEE Std 1500.


A balanced mixture between lectures and small exercises. Course material: lecture notes.


Participants will receive a High Tech Institute course certificate for attending this training.

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Remarks from participants

‘The level of training was very good. Good explanation of DfT in general and specifically for digital IC's.’

Robert Mossel - Nexperia

‘Very useful. Very practical-oriented. Gives an excellent background on test aspects and how-to during different IC development phases. Highly recommended.’

Kasia Nowak - Nexperia

"Good overview of all DfT aspects."

René Segaar – NXP Semiconductors

"The best content for anyone unaware of the DfT (or) a perfect introduction course of DfT."

Leonardo Davinci Darwin – NXP Semiconductors

"I’ve learned a lot about DfT testing and the latest techniques being used nowadays. I grew as a test engineer during this course, in knowledge."

Ragy Magdy – NXP Semiconductors