Integrated circuits are manufactured by a long sequence of high-precision and hence defect prone processing steps. Hence, every individual semiconductor product needs to undergo stringent electrical tests to weed out the defective parts and guarantee outgoing product quality to the customer. The field of ‘Design-for-Test’ (DfT) focuses in the broad sense on developing economically adequate tests for ICs. Those tests need to assure sufficient qualityat acceptable test application costs, corresponding to the target application area (e.g., wireless consumer products have less stringent quality requirements, but also different test cost budgets than medical or aerospace products). As no IC can be released into highvolume production without an adequate manufacturing test, acceptable test development time is also of key importance.
Structural testing, in which tests are generated based on well-accepted defect-abstracting fault models, have largely replaced the traditional functional tests, because they can be generated automatically in relatively short time, achieve objectively better defect coverage, and (in case of failing tests) allow diagnosis algorithms to pinpoint the type and location of the failure root cause. The latter enables automatic high-volume diagnosis to create process learning and yield improvement. One of the main challenges in IC testing is the limited accessibility from the chip pins into theinternal circuitry inside the IC. To improve controllability and observability, extra ‘DfT hardware’ is added to the functional circuitry; this typically amounts to 5-10% of the silicon area. Scan design is the most commonly practiced form of DfT design, whereby a test mode is added in which functional registers are concatenated into one or more shift registers that are accessible from the external test equipment. More advanced forms of DfT hardware include (i) ‘wrappers’ that allow modular testing of increasingly complex chips, (ii) on-chip decompression of test stimuli and compression of test responses, (iii) circuitry that tests parts othe IC itself without the need for external test equipment (‘built-in self-test’ or BIST), and (iv) on-chip features for the benefit of the chip user.
This course, presented by a world-renowned speaker in the field with broad scientific and industrial experience, covers the fundamentals of IC test and DfT. The speaker has presented his course material at many international conferences, as well as to practicing engineers at in-house courses.
€ 1.500,00 excl. VAT
Eindhoven / Nijmegen
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(average score of last 3 editions)
11-05-2020 | 09:00 - 17:00
12-05-2020 | 09:00 - 17:00
13-05-2020 | 09:00 - 17:00
After the course, the participant will:...
After the course, the participant will:
Those involved in design-for-test (DfT) and test of digital integrated circuits (ICs): Digital IC...
Those involved in design-for-test (DfT) and test of digital integrated circuits (ICs): Digital IC design engineers, test and product engineers, fab engineers, test engineers, starting DfT engineers. Also: test researchers, test methodology developers, test tool developers and their managers!
Required background knowledge:
A balanced mixture between lectures and small exercises. Course material: lecture notes....
A balanced mixture between lectures and small exercises. Course material: lecture notes.
Participants will receive a High Tech Institute course certificate for attending this training....
Participants will receive a High Tech Institute course certificate for attending this training.